1. Field of the Invention
The present invention relates to a semiconductor device and it is directed to an insulating gate type bipolar transistor suitable for use as a power supply switching element, for example.
2. Related Background Art
In the field of power semiconductor devices, there is a strong request for low on-voltage and reduction of turn-off loss in addition to enhancement of resistance to high breakdown voltage and availability for larger current. To meet these requirements, IEGT (Injection Enhanced Gate Transistor) has been developed as a further improvement of IGBT (Insulated Gate Bipolar Transistor).
The IEGT is a powering semiconductor device that has realized low on-resistance by rendering the emitter side of an n-type base layer have the peak of carrier concentration rendering it accumulate holes to enhance the efficiency of electron injection from the emitter electrode at the time of turning on.
FIG. 11 is a cross-sectional diagram showing an example of a trench-structured vertical IEGT by a related art. In the IEGT 90 shown here, a p-type collector layer 114 formed on one side of an n-type drift layer (n-type base layer in this example) 100 via an n-type buffer layer 112. On the opposite side of the n-type drift layer 100, a p-type impurity diffusion layer is formed, and a plurality of trenches TR are formed to penetrate the p-type impurity diffusion layer from its surface and reach an inner region of the n-type drift layer 100. Thus, the p-type impurity diffusion layer is divided to main cell regions MC and dummy cell regions DC that are used as p-type main base layers 116 and p-type dummy base layers 118, respectively.
In the surface layer of each p-type main base layer 116 of the main cell region MC, n-type emitter layers 124 are formed selectively. The surface of each p-type dummy base layer 118 of the dummy cell region DC is covered by an insulating film 132 to keep the potential of the p-type dummy base layer 118 floating.
A collector electrode 126 is formed on the p-type collector layer 114. An emitter electrode 128 is formed over the p-type main base layer 116 and the n-type emitter layers 124, and it is connected to the n-type emitter layer 124. In each trench TR, a gate electrode 122 is buried via a gate insulating film 120. As a result of the explained structure, an n-type channel MOSFET for electron injection using the p-type main base layer 116 as a channel region and selectively connecting the n-type emitter layers 124 to the n-type drift layer 100 is formed in each main cell region MC.
In the IEGT 90 shown in FIG. 11, the drift layer 100 of the main cell region MC has the carrier concentration profile having the peak on the part of the emitter electrode 128. Therefore, a sufficiently narrow current path is formed, which connects the n-type drift layer 100 and the emitter electrode 128. As a result, in the on-state of the IEGT 90, the current path increases the resistance to the flow of holes moving from the n-type drift layer 100 toward the emitter electrode 128 through the p-type main base layer 116 of the main cell region MC, and hence limits the discharge of holes to the emitter electrode 128. This results in enhancing the electron injection efficiency from the n-type emitter layer 124 to the n-type drift layer 100, promoting the conductivity modulation of the n-type drift layer 100, and attaining a low on-voltage.
The IEGT 90 shown in FIG. 11, however, involves the problem that the gate voltage runs to overshoot due to so-called negative capacitance, and thereby becomes impossible to control the voltage change rate dV/dt during the on-time. This problem is explained below with reference to FIGS. 12 and 13. In the attached figures, common and equivalent elements are labeled with common reference numerals, and their explanation will be repeated only when necessary.
FIG. 12 is a graph showing an example of voltage and current waveform at the on-time of the IEGT 90 shown in FIG. 11. In this graph, Vge is a gate-emitter voltage, Vce is a collector-emitter voltage, and Ic is a collector current.
In this experiment, the voltage of the IEGT was 1200 V, the voltage applied between the collector and the emitter was 600V, and the gate resistance Rg was 51Ω. Resistance between the p-type dummy base layer 118 and the emitter electrode 128 was 10Ω.
As shown in FIG. 12, the collector-emitter voltage change ratio (dV/dt) of the IEGT 90 shown in FIG. 11 was as large as 20 kV/μs or more in the initial stage of the mirror period t1˜t2 (the period for charging between the gate and the collector with the voltage applied between the gate and emitter), and the waveform vibrated seriously.
FIG. 13 is a graph showing an example of the gate charge characteristics during the on-time of the IEGT 90 shown in FIG. 11, which was obtained by a simulation. In this graph, Vge is the gate-emitter voltage, Vce is the connector-emitter voltage, and Qg is the gate charge. Solid lines show characteristics obtained by dynamic calculation whereas broken lines show characteristics obtained by static calculation (Vce=0V and Vce=600V). Conditions of the IEGT in this simulation are equal to those explained in conjunction with FIG. 12 except the parameters of this simulation.
In the IEGT 90 shown in FIG. 11, the gate-emitter voltage Vge (hereinbelow referred to as Vge(on)) in the mirror period (the period t1–t2 in FIG. 12) is contained in the Vge region where Qg decreases as Vge increases in the static characteristics of Vce=600V. In this case, the waveform of Qg significantly vibrates on the dynamic characteristics as shown in FIG. 13.
The phenomenon of the decrease of Qg with the increase of Vge is called negative capacitance (negative capacitance of the gate) because Cg=dQg/dVge becomes a negative value. The negative capacitance is known as being the cause of bringing about current unbalance upon parallel driving of a semiconductor device (see, for example, Japanese Patent Laid Open (kokai) 2000-40951 and IEEE Device Letters, vol. 18, pp 121–123.)
As seen in the dynamic characteristics of FIG. 13, once the gate emitter voltage Vge (on) in the mirror period enters in the Vge region exhibiting the negative capacitance, the gate-emitter voltage Vge vibrates. This results in increasing the gate-emitter voltage Vge in a short time and permitting rapid electrical conduction of the collector current to invite a large dV/dt.
Through some researches, the Inventor has confirmed that the overshoot of the gate-emitter voltage Vge by such negative capacitance occurs because the potential of the p-type dummy base layer in the dummy cell region is not kept floating completely.
In greater detail, even when the device is designed to keep the potential of the p-type dummy base layer floating as explained before, if the potential in the off-time is fixed near the zero potential via a parasitic resistance caused by the parasitic structure (for example, partial connection to the cell end or the junction terminal end), after the device is turned on, immediately upon the rise of the gate-emitter voltage Vge (on) to the threshold voltage Vth, holes injected thereby suddenly increase the potential of the p-type dummy base layer and ultimately bring about the overshoot of the gate-emitter voltage Vge.
On the other hand, if the emitter contact is formed over the entire surface of the dummy base layer, then the problem of uncontrollability of dV/dt will be overcome. In this case, however, the IE effect will be lost, and the low Vce (sat) characteristics cannot be realized.
To prevent this problem, the use of the structure described in Japanese Patent Laid Open (kokai) 2000-40951, for example, leads to realization of complete floating configuration of the dummy base layer while maintaining the IE effect.
However, in the structure described in Japanese Patent Laid Open (kokai) 2000-40951, if the cell length is changed, for example, when the current capacitance is different, then the structure must be changed as well accordingly. Therefore, the structure disclosed in Japanese Patent Laid Open (kokai) 2000-40951 involves the problem that it lacks compatibility or commonness as a unit structure.